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Energy efficient hardware-software co-synthesis using reconfigurable hardware

[NT 42944] Record Type:	[NT 8598] Electronic resources : [NT 40817] monographic
[NT 47261] Author:	OuJingzhao,
[NT 47354] Secondary Intellectual Responsibility:	Prasanna KumarV. K.,
[NT 47351] Place of Publication:	Boca Raton, Fla
[NT 47263] Published:	Chapman & Hall/CRC;
[NT 47352] Year of Publication:	c2010
[NT 47264] Description:	1 online resource (202 p.)ill :
[NT 47298] Series:	Chapman & Hall/CRC computer and information science series
[NT 47266] Subject:	Field programmable gate arrays - Energy consumption -
[NT 47266] Subject:	Field programmable gate arrays - Design and construction -
[NT 47266] Subject:	Adaptive computing systems - Energy consumption -
[NT 47266] Subject:	System design -
[NT 51458] Online resource:	http://www.crcnetbase.com/isbn/978-1-58488-741-6
[NT 47265] Notes:	Description based on print version record
[NT 51398] Summary:	Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems. Helping overcome these challenges, this book offers solutions for the development of energy efficient applications using FPGAs. It provides a framework for high-level hardware-software application development, describes energy performance modeling for reconfigurable system-on-chip devices, and explores energy efficient designs for various applications. The authors present a two-step rapid energy estimation technique that enables high-level design space exploration and offer a hardware-softw
[NT 50961] ISBN:	9781584887423electronic bk.
[NT 50961] ISBN:	1584887427electronic bk.
[NT 50961] ISBN:	hbk.
[NT 60779] Content Note:	Cover; Title; Copyright; Contents; List of Tables; List of Figures; Acknowledgments; Preface; Chapter 1: Introduction; Chapter 2: Reconfigurable Hardware; Chapter 3: A High-Level Hardware-Software Application Development Framework; Chapter 4: Energy Performance Modeling and Energy Efficient Mapping for a Class of Applications; Chapter 5: High-Level Rapid Energy Estimation and Design Space Exploration; Chapter 6: Hardware-Software Co-Design for Energy Efficient Implementations of Operating Systems; Chapter 7: Concluding Remarks and Future Directions; References; Index

Energy efficient hardware-software co-synthesis using reconfigurable hardware
Ou, Jingzhao

Energy efficient hardware-software co-synthesis using reconfigurable hardware / Jingzhao Ou, Viktor K. Prasanna - Boca Raton, Fla : Chapman & Hall/CRC, c2010. - 1 online resource (202 p.) ; ill. - (Chapman & Hall/CRC computer and information science series).
Cover; Title; Copyright; Contents; List of Tables; List of Figures; Acknowledgments; Preface; Chapter 1: Introduction; Chapter 2: Reconfigurable Hardware; Chapter 3: A High-Level Hardware-Software Application Development Framework; Chapter 4: Energy Performance Modeling and Energy Efficient Mapping for a Class of Applications; Chapter 5: High-Level Rapid Energy Estimation and Design Space Exploration; Chapter 6: Hardware-Software Co-Design for Energy Efficient Implementations of Operating Systems; Chapter 7: Concluding Remarks and Future Directions; References; Index.
Description based on print version record.
Includes bibliographical references (p. 187-195) and index.
ISBN 9781584887423ISBN 1584887427
Field programmable gate arraysField programmable gate arraysAdaptive computing systemsSystem design -- Energy consumption -- Design and construction -- Energy consumption

Prasanna Kumar, V. K.

Energy efficient hardware-software co-synthesis using reconfigurable hardware
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